Figure 1. Mesured frequency transfer curves at the different taps of our artifical cochlea

Figure 2. Idem for the cochlea by Lloyd Watts, et al.

The lower maximum gain of the first 10 (high frequency) stages in fig 1. is a border effect, because the gain accumulates over several stages. The output of the first stages simply are omitted in figure 2. Figure 3. shows the improved regularity of spacing of the best frequencies. The output of this artificial cochlea will be, together with the IHC circuit, the first stage in my electronic auditory pathway.

Figure 3. Best frequency vs. tap number. Left: Our cochlea. Right: Watts' cochlea

Figure 4. The second order stage

Our artificial cochlea basically uses the same second order stages as Watts' (fig 4.), but derivation is obtained using two transconductance amplifiers which calculate the difference between Vout and V1, instead of simply taking a copy of the output current of amplifier A2. The output current of A2 also represents the derivative of Vout, but since the bias current of A2 varies along the cascade, this output current still has to be normalized if you want to have the same maximum value at every output tap. In Watts' cochlea, this normalization uses a resistive line with identical tilt as the other resistive line which controls the bias current of the different stages. This scheme depends on matching of the 2 resistive lines and of the transistors creating the bias currents (NMOS) and the transistors creating the scaled copy of Idif (PMOS). Our solution only depends on matching of transistors of similar type in the 2 additional amplifiers.

Figure 5. Schematic of our artificial cochlea, showing the CLBT's used to create the bias currents

The major improvement in our cochlea stems from the use of Compatible Lateral Bipolar Transistors (CLBTs) to create the exponentially scaled bias currents, which control the time constants and quality factors of the second order stages (fig. 5). The CLBT can be readily made in a standart CMOS process (fig. 6). It uses the well as the base of the bipolar transistor and the drain and source of the MOS transistor as emitter and collector. A second, vertical, bipolar transistor with the substrat as its collector is always associated with a CLBT. Most current will flow to this vertical bipolar. If you are however only interested in the exponential relation between base-emitter voltage and CLBT collector current, as in our case, you don't care about the substrate current.

Figure 6. Bipolar operation of the MOS transistor: carrier flow and symbol

A minor problem with the CLBT is its low output resistance. This can be easily solved using a cascode as shown in figure 7a. Figure 7b shows that the layout of this cascode can be relatively compact. Note that a concentric layout is used with the emmiter in the center. This gives the highest output current for a given base-emmiter voltage.

Figure 7. Schematic and layout of the cascoded CLBT

I've presented a paper [2] on this work at NIPS'95 in Denver. If you want more detail, you can always contact me by email.

REFERENCES
[1] L. Watts, et al., "Improved implementation of the silicon cochlea," IEEE J. Solid-State Circuits, vol. SC-27, pp. 692-700, May 1992.
[2] A. van Schaik, et al., "Improved Silicon Cochlea using Compatible Lateral Bipolar Transistors," to be published in 'Advances in Neural Information Processing Systems 8,' edited by D. Touretzky, et al., MIT press, Cambridge, 1995(6).