Marc A. Viredaz
- Marco Annaratone, Marco Fillo, Kiyoshi Nakabayashi, and Marc
Viredaz.
"The K2 Parallel Processor:
Architecture and Hardware Implementation."
In The 17th Annual International Symposium on Computer
Architecture Conference Proceedings, pp. 92-101, Seattle,
WA (USA), May 1990. IEEE, ACM, IEEE Computer Society Press.
- M. Annaratone, G. zur Bonsen, M. Fillo,
M. Halbherr, R. Rühl, P. Steiner, and
M. Viredaz.
"Architecture, Implementation, and
System Software of K2."
In Arndt Bode (ed.), Distributed Memory Computing,
vol. 487 of Lecture Notes in Computer Science,
pp. 473-484. SpringerVerlag, Berlin Heidelberg (D),
Apr. 1991.
Proceedings of EDMCC2.
- M. Annaratone, G. zur Bonsen, M. Fillo,
M. Halbherr, R. Rühl, P. Steiner, and
M. Viredaz.
"An Overview of the K2
Project."
Physics Reports: A Review Section of Physics Letters,
207(3-5):333-349, Sept. 1991.
Proceedings of the 3rd graduate summer course on computational
physics: Parallel architectures and applications.
- M. Annaratone, M. Fillo, M. Halbherr,
R. Rühl, P. Steiner, and M. Viredaz.
"The K2 Distributed Memory Parallel
Processor: Architecture, Compiler, and Operating System."
In Proceedings: Supercomputing '91, pp. 900-909,
Albuquerque, NM (USA), Nov. 1991. IEEE, ACM, IEEE Computer Society
Press.
- Christian Lehmann, Marc Viredaz, and François
Blayo.
"A Generic Systolic Array Building Block
for Neural Networks with OnChip Learning."
IEEE Transactions on Neural Networks, 4(3):400-407,
May 1993.
Special issue on neural network hardware.
- Marc A. Viredaz.
"MANTRA I: An SIMD Processor Array for
Neural Computation."
In Peter Paul Spies (ed.), Europäischer
Informatik Kongreß Architektur von Rechensystemen
EuroARCH '93, pp. 99-110, Informatik aktuell.
SpringerVerlag, Berlin Heidelberg (D), Oct. 1993.
Proceedings of EuroARCH '93.
- Paolo Ienne and Marc A. Viredaz.
"GENES IV: A BitSerial Processing Element
for a MultiModel NeuralNetwork Accelerator."
In Luigi Dadda and Benjamin Wah (eds.), Proceedings: The
International Conference on ApplicationSpecific Array Processors,
pp. 345-356, Venice (I), Oct. 1993. Euromicro, IEEE Computer
Society Press.
- Marc A. Viredaz and Paolo Ienne.
"MANTRA I: A Systolic
NeuroComputer."
In IJCNN International Joint Conference on Neural Networks,
vol. 3, pp. 3054-3057, Nagoya (J), Oct. 1993. IEEE,
INNS.
- Marc A. Viredaz, Christian Lehmann, François Blayo,
and Paolo Ienne.
"MANTRA: A MultiModel NeuralNetwork
Computer."
In José G. DelgadoFrias and William R. Moore
(eds.), VLSI for Neural Networks and Artificial Intelligence,
pp. 93-102. Plenum Press, New York, NY (USA), 1994.
Proceedings of the 3rd international workshop on VLSI for NNs and
AI.
- Thierry Cornu, Paolo Ienne, Dagmar Niebur, and Marc A.
Viredaz.
"A Systolic Accelerator for Power System
Security Assessment."
In A. Hertz, A. T. Holen, and J.C. Rault (eds.), Proceedings
of the International Conference on Intelligent System Application to Power
Systems, vol. I, pp. 431-438, Montpellier (F),
Sept. 1994.
- Paolo Ienne and Marc A. Viredaz.
"Implementation of Kohonen's
SelfOrganizing Maps on MANTRA I."
In Proceedings of the Fourth International Conference on
Microelectronics for Neural Networks and Fuzzy Systems,
pp. 273-279, Turin (I), Sept. 1994. COREP, Politecnico di
Torino, IEEE Computer Society Press.
- Paolo Ienne and Marc A. Viredaz.
"BitSerial Multipliers and
Squarers."
IEEE Transactions on Computers, 43(12):1445-1450,
Dec. 1994.
- Paolo Ienne and Marc A. Viredaz.
"GENES IV: A BitSerial Processing Element
for a MultiModel NeuralNetwork Accelerator."
Journal of VLSI Signal Processing, 9(3):257-273,
Apr. 1995.
Special issue on applicationspecific array processors.
- Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, and Marc A.
Viredaz.
"Design, Implementation, and Test of a
MultiModel Systolic NeuralNetwork Accelerator."
Scientific Programming, 5(1):47-61, Spring 1996.
- Dieter Scheerer, Eugen Schenfeld, and Marc A. Viredaz.
"MultiDimensional Locks with OnLine
Allocation Schemes."
In Proceedings of the 16th International Conference on
Distributed Computing Systems, pp. 241-248, Hong Kong
(GB), May 1996. IEEE, IEEE Computer Society Press.
- Marco Annaratone, Georg zur Bonsen, Marco Fillo, Kiyoshi
Nakabayashi, Claude Pommerell, Roland Rühl, Peter Steiner, and Marc
Viredaz.
"Ein ParallelComputer mit
verteiltem Speicher: Das K2Projekt."
Bulletin SEV/VSE, 81(17):11-18, Aug. 1990.
- Christian Lehmann, François Blayo, and Marc
Viredaz.
"MANTRA I - Autonomous NeuralSlice
Machine for Kohonen's SelfOrganized Feature Maps."
In Working Group 4 (WG4) Workshop on Massively Parallel
Computing, Leysin (CH), Mar. 1992. COST 229.
- Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, and
Marc A. Viredaz.
"MANTRA Project - Part A: Design,
Implementation and Test of a MultiModel Systolic Neural Network
Accelerator."
In Priority Programme Informatic Research Information Conference
Module 3, pp. 113-120, Zurich (CH), Nov. 1994.
- Marco Annaratone, Marco Fillo, Kiyoshi Nakabayashi, and Marc
Viredaz.
"The K2 Parallel Processor: Architecture
and Hardware Implementation."
Technical report no. 89/23, IIS, ETH, Zurich (CH), 1989.
Submitted to: ISCA90.
- Marc A. Viredaz.
"The Serial Network Interface Controller
(SNIK) of K2: Hardware Description."
Technical report no. 90/16, IIS, ETH, Zurich (CH), Oct. 1990.
- Marc A. Viredaz.
"Design of Test Routines for the
SNIK."
Technical report no. 90/17, IIS, ETH, Zurich (CH), Oct. 1990.
- Peter Steiner and Marc A. Viredaz.
"The Serial Network Interface Controller
(SNIK) of K2."
Technical report no. 91/14, IIS, ETH, Zurich (CH), Oct. 1991.
- Marc A. Viredaz.
"The Mass Storage Controller (MSC) of
K2."
Technical report no. 91/15, IIS, ETH, Zurich (CH), Dec. 1991.
- Marc A. Viredaz.
"Design Specifications for the Backplane of
K2."
Technical report no. 91/16, IIS, ETH, Zurich (CH), Oct. 1991.
- M. Annaratone, M. Fillo, M. Halbherr,
R. Rühl, P. Steiner, and M. Viredaz.
"The K2 Distributed Memory Parallel
Processor: Architecture, Compiler, and Operating System."
Technical report no. 91/20, IIS, ETH, Zurich (CH), Nov. 1991.
Reprinted from: Proceedings: Supercomputing '91.
- Marc A. Viredaz.
"Architectures
parallèles."
In J.D. Nicoud, R. Beuchat, E. Laurentiu, C. Marguerat, and
M. Viredaz, Microprocesseurs II.
LAMI, EPFL, Lausanne (CH), 1st edition, Apr. 1992.
- Marc A. Viredaz, Christian Lehmann, François Blayo,
and Paolo Ienne.
"MANTRA: A MultiModel NeuralNetwork
Computer."
Technical report no. 92/6, DI, EPFL, Lausanne (CH), July 1992.
- Paolo Ienne and Marc A. Viredaz.
"BitSerial Input and Output Multipliers and
Squarers."
Technical report no. 92/7, DI, EPFL, Lausanne (CH), Oct. 1992.
- Marc A. Viredaz.
"MANTRA I: An SIMD Processor Array for
Neural Computation."
Technical report no. 93/23, DI, EPFL, Lausanne (CH),
Feb. 1993.
Submitted to: EuroARCH '93.
- Marc A. Viredaz.
"The MANTRA I Prototype Machine: Hardware
Description."
MANTRA internal report no. 93/2, EPFL, Lausanne (CH), Sept. 1993.
- Anne GuérinDugué and Marc A. Viredaz.
"Machines pour réseaux de neurones
artificiels."
Cours postgrade en informatique: Réseaux de neurones biologiques et
artificiels, EPFL, Lausanne (CH), Sept. 1993.
- Dieter Scheerer, Eugen Schenfeld, and Marc A.
Viredaz.
"MultiDimensional Locks with Online
Allocation Schemes."
Technical report no. 95157, NEC Research Institute, Princeton, NJ (USA),
Oct. 1995.
- Marc A. Viredaz.
"The Itsy Pocket Computer Version 1.5:
User's Manual."
Technical note TN54, WRL, Compaq, Palo Alto, CA (USA),
July 1998.
Revision 1.0.
- Marc A. Viredaz.
"The Memory DaughterCard Version 1.5:
User's Manual."
Technical note TN55, WRL, Compaq, Palo Alto, CA (USA),
July 1998.
Revision 1.0.
Marc A. Viredaz,
Compaq
WRL
(viredaz@pa.dec.com)